1. Field of the Invention
The technology relates to Electronic Design Automation (EDA) tools, computer instructions implementing the EDA tools, computers executing the EDA tools, and the circuits designed by the EDA tools.
2. Description of Related Art
Previous attempts to solve the problem of restructuring on a placed netlist have failed for one or more of the following reasons:                Exploring the solutions costs a lot of runtime.        Four engines need to work together (logic structuring, mapping, sizing and placement)        Accepted solutions in their timing context did not carry through to the end of the layout.        Incremental placement on the newly created cells is hard.        
Previous solutions fail to get the Quality of Results (QOR) at a small runtime. Previous solutions have to introduce runtime controls that penalize the QOR. The main issue is that the algorithm iterates for a long time and the solutions have poor criteria to determine whether a set of cells should be structured again if the set of cells remain critical after a round of optimization.
Optimization flows from logic equations, to logic gates, to layout, in decreasing levels of abstraction (optimization targets for example the clock frequency of a circuit). As the flow progresses from equations to layout, context is more accurate, but delay optimizations become harder. As the optimization flow progresses, runtime for a unit gain increases, accuracy of estimates increases and gain potential of a change decreases.
Prior techniques of determining whether to halt optimization used arrival and required time information for pins. However, the mere fact that the arrival and required time information differs between two pins, or the same pin under different optimizations, fails to indicate the presence or absence of a need to further optimize the pins.